Semiconductor dice or chips are typically individually packaged for use in plastic or ceramic packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One type of semiconductor package is referred to as a "chip scale package". Chip scale packages are also referred to as "chip size packages", and the dice are referred to as being "minimally packaged". Chip scale packages can be fabricated in "uncased" or "cased" configurations. Uncased chip scale packages have a "footprint" (peripheral outline) that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, glass or FR-4. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
One aspect of chip scale packages is that the substrates and external contacts are difficult to fabricate. In addition, reliable electrical connections must be made to die contacts (e.g., bond pads) on the die contained within the package. Further, electrical paths must be formed on the substrate between the die contacts and the external contacts. With increasing contact densities, forming these electrical paths becomes increasingly expensive, and requires more complex fabrication processes. Accordingly, improved fabrication processes for chip scale packages are needed.
Another aspect of chip scale packages is the mounting of the packages to supporting substrates, such as printed circuit boards, and ceramic modules. This is sometimes referred to as the second level of packaging. Typically, the packages are surface mounted by reflowing the external contacts on the package to corresponding contacts on the supporting substrate. It would be advantageous for chip scale packages to be capable of denser second level packaging arrangements than conventional surface mount arrangements.
In view of the foregoing, the present invention is directed to an improved chip scale package and method of fabrication.